module s5kr00fx_ctrl
			(
/*
================================================================================
Beggining of user changeable code
Part 1. IO description
*/
			 clock, resetn,

			 RX, TX, SEL,

			 ALL_RX, ALL_TX,

			 P1, VOG,
			 RST_SHR,

			 V_CLK, PHI_VIN,
			 PHI_VOUT,
			 
			 H_CLK, PHI_HIN,
			 PHI_HOUT,
			
			 VVO, VVL, VVH,
			
			 DIN_DAC, SCLK_DAC,
			 PREn_DAC,
			 FS_DAC, MODE_DAC, LDACn_DAC,
			
			 RESETn_ADC, CSn_ADC,
			 CONVSTn_ADC, RDn_ADC,
			 BUSYn_ADC,
			 MODE1_ADC, MODE2_ADC,
			 WRITE_ADC, CLIP_ADC, NAP_ADC,
			 STBY_ADC,
			
			 ADC_DB,
			
			 POD_CLKn, VSYNC, HSYNC,
			 POD_DB,
			
			 RESETn_CIS, EN_CIS,
			 SCL, SDA,

			 DIPSWn
			);

input			clock, resetn;

output			RX, TX, SEL;
output			ALL_RX, ALL_TX;
output			P1, VOG;
output			RST_SHR;

output			V_CLK, PHI_VIN;
input			PHI_VOUT;

output			H_CLK, PHI_HIN;
input			PHI_HOUT;

output			VVO, VVL, VVH;

output			DIN_DAC, SCLK_DAC;
output			PREn_DAC;
output			FS_DAC, MODE_DAC, LDACn_DAC;

output			RESETn_ADC, CSn_ADC;
output			CONVSTn_ADC, RDn_ADC;
input			BUSYn_ADC;
output			MODE1_ADC, MODE2_ADC;
output			WRITE_ADC, CLIP_ADC, NAP_ADC;
output			STBY_ADC;

input	[12:0]	ADC_DB;

output			POD_CLKn, VSYNC, HSYNC;
output	[15:0]	POD_DB;

input			RESETn_CIS, EN_CIS;
input			SCL, SDA;
input	[7:0]	DIPSWn;

/*
End of user changeable code
Part 1.
================================================================================
*/

/*
================================================================================
Beggining of user changeable code
Part 2. Definition of microprocessor generated internal control signal
*/

/* Definition of wires for logic analyzer pod registers */
wire			load_podreg;

/*
End of user changeable code
Part 2.
================================================================================
*/

/* Definition of wires for interfacing processor core */
wire	[11:0]	INITA;
wire	[15:0]	INITB;

wire	[3:0]	PERIINIT;
wire	[3:0]	PERIADDRREG;
wire	[7:0]	PERICTRLREG;
wire	[15:0]	PERIVALREG;

wire	[7:0]	INTFLAG;

wire	[11:0]	PORTA;
wire	[15:0]	PORTB;

wire	[7:0]	rDIPSW;

wire	[27:0]	rA, rB;			// For direct accessing registers in microprocessor

proccore	proccore_inst (.clock(clock), .resetn(resetn),
						   .rDIPSW(rDIPSW),
						   .INITA(INITA), .INITB(INITB),
			 			   .PORTA(PORTA), .PORTB(PORTB),
			 			   .rA(rA), .rB(rB),

			 			   .INTFLAG(INTFLAG),
			 			   .PERIINIT(PERIINIT), .PERIADDRREG(PERIADDRREG),
			 			   .PERICTRLREG(PERICTRLREG), .PERIVALREG(PERIVALREG));

dipswreg	DIPSWREG1	(.clock(clock), .resetn(resetn), .DATAn(DIPSWn), .Q(rDIPSW));

/*
================================================================================
Beggining of user changeable code
Part 3. Assignment of PORTA[11:0] and PORTB[15:0]
*/

assign		RST_SHR			= PORTA[11];
assign		PHI_VIN			= PORTA[10];
assign		V_CLK			= PORTA[9];
assign		SEL				= PORTA[8];

assign		RX				= PORTA[7];
assign		TX				= PORTA[6];
assign		PHI_HIN			= PORTA[5];
assign		H_CLK			= PORTA[4];

assign		VSYNC			= PORTA[3];
assign		HSYNC			= PORTA[2];
assign		CONVSTn_ADC		= PORTA[1];
assign		POD_CLKn		= PORTA[0];


assign		ALL_RX			= PORTB[15];
assign		ALL_TX			= PORTB[14];
assign		P1				= PORTB[13];
assign		VOG				= PORTB[12];
assign		VVO				= PORTB[11];
assign		VVL				= PORTB[10];
assign		VVH				= PORTB[9];

assign		INITA			= 12'h882;		// Initial value of PORTA
assign		INITB			= 16'h0000;		// Initial value of PORTB

/*
End of user changeable code
Part 3.
================================================================================
*/

/*
================================================================================
Beggining of user changeable code
Part 4. Instantiation of peripheral logics
*/
wire			init_dac0;
wire			idle_dac0;
wire			init_adc0, init_adc1;		// Initiating signal for serial ADCs
wire			idle_adc0, idle_adc1;		// Idlee signal of serial ADCs

wire			sSCLK_DAC, sFS_DAC, sDIN_DAC;
wire			sLDACn_DAC, sPREn_DAC, sMODE_DAC;

opndrn	OPNDRN0 (.in(sSCLK_DAC),	.out(SCLK_DAC));	// Define all of DAC control
opndrn	OPNDRN1 (.in(sFS_DAC),		.out(FS_DAC));		// signal as open drain because
opndrn	OPNDRN2 (.in(sDIN_DAC),		.out(DIN_DAC));		// tlv56xx has different operating
opndrn	OPNDRN3 (.in(sLDACn_DAC),	.out(LDACn_DAC));	// voltage than ACEX1k series FPGA.
opndrn	OPNDRN4 (.in(sPREn_DAC),	.out(PREn_DAC));
opndrn	OPNDRN5 (.in(sMODE_DAC),	.out(MODE_DAC));

tlv56xxctrl	tlv56xxctrl_inst (.clock(clock), .resetn(resetn),
							  .start(init_dac0), .busyn(idle_dac0),
							  .ADDR(PERIVALREG[15:12]), .DATA(PERIVALREG[11:0]),
							  .SCLK(sSCLK_DAC), .FS(sFS_DAC), .DOUT(sDIN_DAC),
							  .LDACn(sLDACn_DAC), .PREn(sPREn_DAC), .MODE(sMODE_DAC));
/*
End of user changeable code
Part 4.
================================================================================
*/

/*
================================================================================
Beginning of user changeable code
Part 5. Assignment of peripheral initiating signal
*/

assign		init_adc0 = PERIINIT[0];
assign		init_adc1 = PERIINIT[1];
assign		init_dac0 = PERIINIT[2];

/*
Beginning of user changeable code
Part 5. Assignment of peripheral initiating signal
================================================================================
*/

wire	[15:0]	DATA_DB;

/*
================================================================================
Beginning of user changeable code
Part 7. Assignment of logic analyzer pod data
*/

assign		DATA_DB = {3'b0, ADC_DB};

/*
End of user changeable code
Part 7.
================================================================================
*/

podreg		PODREG1		(.clock(clock), .resetn(resetn), .load(POD_CLKn),
						 .DATA(DATA_DB),
						 .Q(POD_DB));

/*
================================================================================
Beginning of user changeable code
Part 8. Assignment of interrupt flag (INTFLAG)
*/

assign		INTFLAG = {4'b0, idle_dac0, idle_adc1, idle_adc0, 1'b0};

/*
End of user changeable code
Part 8.
================================================================================
*/

endmodule